The present invention relates to semiconductor device manufacturing, and more particularly to a method of lowering the gate resistance of a metal oxide semiconductor field effect transistor (MOSFET), while simultaneously reducing silicon consumption in the source/drain regions.
In the semiconductor industry, there is a need for increasing the gate density and operating speed of integrated circuits (ICs). One way to accomplish increased gate density and operating speed is to decrease the minimum feature size of the MOSFETs within the IC. In typical MOSFET fabrication processes, the formation of source/drain regions by ion implantation and annealing causes some lateral diffusion of dopant beneath the gate region. The extent of lateral diffusion can be limited by providing sidewall spacers about the gate region prior to implanting the source/drain regions. In addition to restricting the lateral diffusion of the source/drain regions under the gate region, the lateral diffusion must also be limited by controlling the depth of the source/drain regions. Typically, the smaller feature sizes used to improve gate density and operating speed also require increasingly shallow source/drain regions.
Another requirement for IC fabrication is the formation of ohmic contacts on the source/drain regions. Ohmic contacts are typically fabricated in the prior art by forming a silicide layer atop the source/drain regions. In addition, the sheet resistance of the Si-containing gate interconnect surfaces must be lowered in order to reduce RC delay across the MOSFET gate. Lower sheet resistance of the gate region is also achieved by forming a silicide layer atop the uppermost Si-containing gate conductor layer.
In typical prior art processes, the ohmic contacts and the silicide atop the gate conductor are formed by deposition of a metal layer over the Si-containing surfaces (i.e., atop the source/drain regions and the uppermost surface of a Si-containing gate conductor) and annealing which converts the metal layer and nearby Si-containing surfaces into a silicide layer. During this process which is referred to in the art as silicidation, some amount of silicide forms downward into the source/drain regions. This causes a problem in cases where the source/drain regions are very shallow, and the silicide (i.e., ohmic contact) thickness is sufficiently large since the silicide may penetrate substantially or completely through the source/drain regions. Substantial or complete penetration of the silicide through the source/drain regions may result in excessive junction leakage during operation causing device failure.
In order to reduce such junction leakage, the amount of metal used in forming the silicide layer of the source/drain regions may be reduced. Lower amounts of deposited metal typically correlate to a thinner silicide layer being formed. Although it is desirable to have thin silicide formation atop the source/drain regions, the reduced thickness of the silicide layer is generally not warranted atop the gate regions since it leads to increased sheet resistance of the gate interconnects. This increased sheet resistance, in turn, will increase the RC delay across the MOSFET gate thereby reducing high frequency circuit performance.
U.S. Pat. No. 6,060,387 to Shepela, et al. provides a process for forming a transistor in an IC where two silicide formation steps, which are independent of each other, are employed in forming a thin silicide layer over the source/drain regions and a thicker silicide layer over the gate conductor. Specifically, in this prior art process, a structure including a gate interconnect and source/drain regions is first provided. A first silicide layer is provided on the surface of the source/drain regions. A gap fill layer having a thickness that is greater than the height of the gate interconnect structure is deposited, and thereafter the gap fill layer is planarized using chemical-mechanical polishing (CMP) to expose top surfaces of the interconnect. A second relatively thick silicide layer is formed on the top surface of the gate interconnect. The process disclosed in Shepela, et al. reportedly provides a sufficiently low resistance, thin silicide layer over the source/drain regions, while also creating a lower resistance, relatively thicker silicide layer over the gate interconnect material.
U.S. Pat. No. 6,153,485 to Pey, et al. discloses a method where source/drain silicide contacts are formed in a separate silicide step than the gate silicide contacts. In accordance with the process disclosed in the ""485 patent, a TiSi2 layer is formed over the source/drain regions while the gate electrode is protected by a silicon nitride cap layer. An interlevel dielectric (ILD) layer is formed over the source/drain regions, planarized via CMP, and thereafter, the ILD layer, silicon nitride cap layer and spacers on the sidewalls of the gate electrodes are etched back. A second silicide layer is then formed atop the exposed gate electrode surfaces.
In both prior art processes mentioned above, CMP or another like planarization processing step is required to provide a thick silicide layer atop the gate conductor region. The use of CMP or another like planarization process is undesirable, not only because it adds additional processing steps and cost to the overall fabrication process, but it is oftentimes difficult to stop the planarization process on the uppermost surface of the gate conductor material.
In view of the above problems with prior art processes of forming a semiconductor structure having a thin silicide located atop source/drain regions and a thick silicide region located atop the gate region, there is a continued need to provide a new and improved method which avoids the use of CMP or another like planarization method in forming such a structure.
One object of the present invention is to provide a method of fabricating a semiconductor structure in which a thick silicide region is formed atop the gate region, while simultaneously obtaining a thin silicide region atop the source/drain regions.
Another object of the present invention is to provide a method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions.
A further object of the present invention is to provide a method of fabricating a semiconductor structure having a thin silicide region formed atop the source/drain regions and a thicker silicide region formed atop the gate region which employs processing steps which are compatible with existing MOSFET manufacturing processes.
A yet further object of the present invention is to provide a method of fabricating a semiconductor structure having a thin silicide layer formed atop the source/drain regions and a thicker silicide region formed atop the gate region which does not require using CMP or another like planarization process in forming the thicker silicide region atop the gate region.
These and other objects and advantages are obtained in the present invention by first forming a structure which includes self-aligned silicide regions atop the source/drain diffusion regions and the gate region. A non-reactive film and a planarizing film are then applied to the structure containing the self-aligned silicide regions and thereafter a thicker silicide region, as compared to the self-aligned silicide region located atop the source/drain regions, is formed on the gate region.
In broad terms, the method of the present invention comprises the steps of:
providing a MOSFET structure comprising first silicide regions of a first thickness atop source/drain diffusion regions and a patterned gate region;
forming a non-reactive film on said structure including atop said patterned gate region;
forming a planarizing film on said structure, said planarizing film is substantially coplanar with an exposed upper horizontal surface of said non-reactive film that is present atop the patterned gate region;
selectively removing the exposed portion of said non-reactive film so as to expose the first silicide region present atop the patterned gate region;
selectively removing the planarizing film from said structure; and
forming a second silicide region atop the patterned gate region that is thicker than the first silicide region located atop the source/drain diffusion regions.
The present invention also provides a semiconductor structure which is formed during the process of the present invention. Specifically, the inventive structure comprises:
a semiconductor substrate having at least one patterned gate region located on a surface thereon, said substrate containing source/drain diffusion regions abutting said at least one patterned gate region;
silicide regions located atop said source/drain diffusion regions and an upper portion of said at least one patterned gate region;
a non-reactive film located atop the silicide regions as well as exposed vertical portions of said at least one patterned gate region; and
a planarizing film located atop said non-reactive film, wherein said planarizing film has an upper horizontal surface that is coplanar with an upper surface of said non-reactive film which overlays said at least patterned gate region.